Ad hoc flash memory reference cells

ABSTRACT

In a nonvolatile memory, that includes cells organized in a plurality of bit lines and a plurality of word lines, user data are stored in respective portions of each of two of the word lines. Control information is stored in a cell that is common to one of the bit lines and one of the two word lines. A cell that is common to the bit line and the other word line is used as a reference cell. A flash memory, that includes a plurality of primary cells and a plurality of spare cells, is interrogated to determine which spare cells have been used to replace respective primary cells. At least some of the other spare cells are used as reference cells.

This patent application claims the benefit of U.S. Provisional PatentApplication No. 61/074,705, filed Jun. 23, 2008

FIELD AND BACKGROUND OF THE INVENTION

The present invention relates to flash memories and, more particularly,to the use, as reference cells, of flash memory cells not initiallyintended to be used for that purpose.

Flash memories are structured as rectangular arrays of memory cells. Thecells are arranged in orthogonal bit lines and word lines. One or morebits of data are written to each cell by injecting sufficient electricalcharge into a floating gate of the cell to place the cell's thresholdvoltage within a range of threshold voltages that represents the valueof that bit or of those bits. A flash memory cell is read by comparingits threshold voltage to reference voltages that mark the boundariesbetween threshold voltage ranges. In the case of a NOR flash memory, thecells may be written and read individually. In the case of a NAND flashmemory, the cells are written and read one page at a time, with eachword line including a small integral number (typically one or two,generally no more than four) of pages. The word lines are groupedfurther into blocks, such that cells are erased an entire block at atime.

For historical reasons, writing data to a flash memory cell also iscalled “programming” the cell.

One of the most disturbing issues in operation of Flash memories is thechanging of cells' threshold voltage with the time, due to leakage ofcharge from the cells' floating gates. This phenomenon also is known as“data retention shift”. Excess data retention shift may result in errorswhen reading data from a flash memory, if reading reference voltagelevels have not been adjusted in accordance with this shift. However,how can one know how much the cell threshold voltage have been shifteddue to data retention shift, or, in other words, how much should thereading reference voltages be adjusted?

One conventional approach for addressing this issue is to assign acertain number of cells in each page as reference cells, to programthese cells with a-priori known data, and to “sense” these cells'voltage thresholds in order to evaluate the amount of shift that causedby data retention. Implementing such reference cells in a flash memorysystem greatly improves the system's ability to cope with the dataretention shift phenomenon.

However, in order to be able to get a reliable estimate of the dataretention shift using such reference cells, the number of such cells foreach flash page is not small. At least several tens of reference cellsare required for each voltage level. This is a significant number ofcells, especially in “multi-level-cell” flash memory devices that storemore than one bit per cell. Adding such a significant number of cells toa flash memory page obviously increases the flash die size and,therefore, the cost of the flash silicon substrate.

Hence, it would be highly advantageous to be able to implement referencecells without increasing the flash memory die size.

SUMMARY OF THE INVENTION

One embodiment provided herein is a method of managing a nonvolatilememory that includes a plurality of cells organized in a plurality ofbit lines and a plurality of word lines, the method comprising: (a)storing user data in respective portions of the cells of each of two ofthe word lines; and (b) in one of the bit lines that is shared by thetwo word lines: (i) storing control information in a cell common to theone bit line and a first of the two word lines, and (ii) using a cellcommon to the one bit line and a second of the two word lines as areference cell.

Another embodiment provided herein is a controller, for a flash memorythat includes a plurality of cells organized in a plurality of bit linesand a plurality of word lines, the controller being operative: (a) tostore user data in respective portions of the cells of each of two ofthe word lines; and (b) in one of the bit lines that is shared by thetwo word lines: (i) to store control information in a cell common to theone bit line and a first of the two word lines, and (ii) to use a cellcommon to the one bit line and a second of two word lines as a referencecell.

Another embodiment provided herein is a flash memory device comprising:(a) a flash memory including a plurality of cells organized in aplurality of bit lines and a plurality of word lines; and (b) acontroller operative: (i) to store user data in respective portions ofthe cells of each of two of the word lines, and (ii) in one of the bitlines that is shared by the two word lines: (A) to store controlinformation in a cell common to the one bit line and a first of the twoword lines, and (B) to use a cell common to the one bit line and asecond of two word lines as a reference cell.

Another embodiment provided herein is a system comprising: (a) a flashmemory including a plurality of cells organized in a plurality of bitlines and a plurality of word lines; (b) a host, of the flash memory,including: (i) a memory for storing code for managing the flash memoryby steps including: (A) storing user data in respective portions of thecells of each of two of the word lines, and (B) in one of the bit linesthat is shared by the two word lines: (I) storing control information ina cell common to the one bit line and a first of the two word lines, and(II) using a cell common to the one bit line and a second of the twoword lines as a reference cell, and (ii) a processor for executing thecode.

Another embodiment provided herein is a computer-readable storage mediumhaving embodied thereon computer-readable code for managing a flashmemory that includes a plurality of cells organized in a plurality ofbit lines and a plurality of word lines, the computer-readable codecomprising: (a) program code for storing user data in respectiveportions of the cells of each of two of the word lines; and (b) programcode for, in one of the bit lines that is shared by the two word lines:(i) storing control information in a cell common to the one bit line anda first of the two word lines, and (ii) using a cell common to the onebit line and a second of the two word lines as a reference cell.

Another embodiment provided herein is a method of managing a flashmemory that includes a plurality of primary cells and a plurality ofspare cells, the method comprising: (a) interrogating the flash memoryto determine which spare cells have been used to replace respectiveprimary cells; and (b) using, as reference cells, at least a portion ofa remainder of the spare cells.

Another embodiment provided herein is a controller, for a flash memorythat includes a plurality of primary cells and a plurality of sparecells, the controller being operative: (a) to interrogate the flashmemory to determine which spare cells have been used to replacerespective primary cells; and (b) to use, as reference cells, at least aportion of a remainder of the spare cells.

Another embodiment provided herein is a flash memory device comprising:(a) a flash memory including a plurality of primary cells and aplurality of spare cells; and (b) a controller operative: (i) tointerrogate the flash memory to determine which spare cells have beenused to replace respective primary cells, and (ii) to use, as referencecells, at least a portion of a remainder of the spare cells.

Another embodiment provided herein is a system, comprising: (a) a flashmemory including a plurality of primary cells and a plurality of sparecells; and (b) a host, of the flash memory, including: (i) a memory forstoring code for managing the flash memory by steps including: (A)interrogating the flash memory to determine which spare cells have beenused to replace respective primary cells, and (B) using, as referencecells, at least a portion of a remainder of the spare cells, and (ii) aprocessor for executing the code.

Another embodiment provided herein is a computer-readable storage mediumhaving embodied thereon computer-readable code for managing a flashmemory that includes a plurality of primary cells and a plurality ofspare cells, the computer-readable code comprising: (a) program code forinterrogating the flash memory to determine which spare cells have beenused to replace respective primary cells; and (b) program code forusing, as reference cells, at least a portion of a remainder of thespare cells.

Two general methods are presented herein for ad hoc designation ofreference cells of a memory. The first method is not restricted to flashmemories, but is directed at managing any nonvolatile memory thatincludes a plurality of cells organized in a plurality of bit lines anda plurality of word lines. The second method is specific to flashmemories, and is directed to managing a flash memory that includes aplurality of primary cells and a plurality of spare cells.

According to the first general method, user data are stored inrespective portions of the cells of each of two of the word lines. Inone of the bit lines that is shared by the two word lines, controlinformation is stored in a cell common to the bit line and to one of theword lines, and a cell that is common to the bit line and to the otherword line is used as a reference cell for reading at least one othercell of the memory. Note that the two cells in question are cells thatare not used to store user data.

Preferably, the user data are stored only in cells other than the cellsof the one bit line that includes the reference cell. For example, inthe example presented in the preferred embodiments below, the cells thatare used to store user data are the cells of section 108, the cell thatis used to store control information is a cell of section 110, and thecell that is used as a reference cell is another cell of section 110.

In some embodiments, the two word lines are in the same, erase block ofthe nonvolatile memory. In such embodiments, preferably, the controlinformation is block-level management information for managing theshared block, as opposed to e.g. page-level management information formanaging a page that is stored in one of the word lines. In otherembodiments, the two word lines are in separate respective erase blocksof the nonvolatile memory. In some such embodiments, the controlinformation is error correction code information.

According to the second general method, the flash memory is interrogatedto determine which spare cells have been used to replace respectiveprimary cells. At least a portion of the remaining spare cells (i.e.,one or more spare cells that have not been used to replace respectiveprimary cells) is used as reference cells for reading at least some ofthe primary cells that have not been replaced and/or for reading atleast some of the spare cells that have been used to replace primarycells.

A memory controller that implements the first general method isoperative to store user data in respective portions of the cells of eachof two of the word lines, and, in one of the bit lines that is shared bythe two word lines, to store control information in a cell common to thebit line and to one of the word lines, and to use a cell common to thebit line and to the other word line as a reference cell.

A flash memory controller that implements the second general method isoperative to interrogate the flash memory to determine which spare cellshave been used to replace respective primary cells, and to use, asreference cells, at least a portion of the other spare cells.

A memory device that corresponds to one of the two general methodsincludes a memory and a controller that manages the memory according tothe relevant general method.

A system that corresponds to one of the two general methods includes afirst memory, a second memory and a processor. The second memory is forstoring code for implementing the relevant general method to manage thefirst memory. The processor executes the code. A computer readablestorage medium that corresponds to one of the two general methods hasembedded thereon computer code for managing a memory using the relevantgeneral method.

BRIEF DESCRIPTION OF THE DRAWINGS

Various embodiments are herein described, by way of example only, withreference to the accompanying drawings, wherein:

FIG. 1 is a high-level schematic block diagram of a flash memory devicein which ad hoc designation of reference cells is effected by acontroller;

FIG. 2 shows some details of one exemplary memory cell array of a flashmemory device of FIG. 1;

FIG. 3 is a high-level block diagram of a system in which ad hocdesignation of reference cells of a flash memory is effected bysoftware.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The principles and operation of a flash memory according to the presentinvention may be better understood with reference to the drawings andthe accompanying description.

Referring now to the drawings, FIG. 1 is a high-level schematic blockdiagram of a flash memory device. A memory cell array 1 including aplurality of memory cells M arranged in a matrix is controlled by acolumn control circuit 2, a row control circuit 3, a c-source controlcircuit 4 and a c-p-well control circuit 5. Column control circuit 2 isconnected to bit lines (BL) of memory cell array 1 for reading datastored in the memory cells (M), for determining a state of the memorycells (M) during a writing operation, and for controlling potentiallevels of the bit lines (BL) to promote the writing or to inhibit thewriting. Row control circuit 3 is connected to word lines (WL) to selectone of the word lines (WL), to apply read voltages, to apply writingvoltages combined with the bit line potential levels controlled bycolumn control circuit 2, and to apply an erase voltage coupled with avoltage of a p-type region on which the memory cells (M) are formed.C-source control circuit 4 controls a common source line connected tothe memory cells (M). C-p-well control circuit 5 controls the c-p-wellvoltage.

The data stored in the memory cells (M) are read out by column controlcircuit 2 and are output to external I/O lines via I/O data lines and adata input/output buffer 6. Program data to be stored in the memorycells are input to data input/output buffer 6 via the external I/Olines, and are transferred to column control circuit 2. The external I/Olines are connected to a controller 20.

Command data for controlling the flash memory device are input to acommand interface connected to external control lines which areconnected with controller 20. The command data inform the flash memoryof what operation is requested. The input command is transferred to astate machine 8 that controls column control circuit 2, row controlcircuit 3, c-source control circuit 4, c-p-well control circuit 5 anddata input/output buffer 6. State machine 8 can output a status data ofthe flash memory such as READY/BUSY or PASS/FAIL.

Controller 20 is connected or connectable with a host system such as apersonal computer, a digital camera, a personal digital assistant. It isthe host which initiates commands, such as to store or read data to orfrom the memory array 1, and provides or receives such data,respectively. Controller 20 converts such commands into command signalsthat can be interpreted and executed by command circuits 7. Controller20 also typically contains buffer memory for the user data being writtento or read from the memory array. A typical memory device includes oneintegrated circuit chip 21 that includes controller 20, and one or moreintegrated circuit chips 22 that each contains a memory array andassociated control, input/output and state machine circuits. The trend,of course, is to integrate the memory array and controller circuits ofsuch a device together on one or more integrated circuit chips. Thememory device may be embedded as part of the host system, or may beincluded in a memory card that is removably insertable into a matingsocket of host systems. Such a card may include the entire memorydevice, or the controller and memory array, with associated peripheralcircuits, may be provided in separate cards.

FIG. 2 shows some details of one exemplary memory cell array 1. Thememory cell array 1 of FIG. 2 includes three erase blocks 102. Eacherase block 102 includes four word lines 106. (Erase blocks normallyinclude many more than four word lines. The example of FIG. 2 shows fourword lines per erase block for simplicity.) Perpendicular to word lines106 are many bit lines 104. (The ellipses in FIG. 2 mean that there aremany more bit lines 104 between the indicated bit lines 104.) Thesquares at the intersections of word lines 106 and bit lines 104represent memory cells. Thus, as described above, the memory cells ofarray 1 are a rectangular array of cells, with each column of cells on ashared bit line 104 and each row of cells on a shared word line 106.

Memory cell array 1 of FIG. 2 is divided into three sections, with thecells of each section being used for a different purpose. Section 108 isa data section. The cells of section 108 are used to store data. Section110 is a control section. The cells of section 110 are used to storecontrol and management information such as error correction code (ECC)bits for the data in section 108. Section 112 is a redundant section.The cells of section 112 are called “redundant column cells” and areused to compensate for (i.e., to replace) bad bit lines 104 in sections108 and 110. (In some of the appended claims, the cells of section 108and 110 are called “primary cells” and the cells of section 112 arecalled “spare cells”.) During the initial testing of the device of FIG.1, bad bit lines 104 are detected and are “replaced” by good bit lines104 of section 112 by being remapped to good bit lines 104 of section112. This remapping information is recorded in the device of FIG. 1.

Flash memory cell array 1 is designed with enough redundant bit lines104 in section 112 to cover even rare cases, in which a significantnumber of bit lines 104 in sections 108 and 110 are bad. Experienceshows, however, that in most cases only a small number of bit lines 104have to be remapped bit lines. Therefore, most of the redundant bitlines 104 are statistically unused, and are free to be used as referencecells.

In order for the cells of redundant bit lines 104 to be used asreference cells, controller 20 is configured to perform the following,in normal mode of operation:

-   -   Get column remapping information    -   Enable access (read and program) to redundant bit lines 104.

It should be noted, that conventional flash memory devices alreadyenable these controller actions in special operation modes, intended forflash memory device testing.

The number of flash memory cells that are used as reference cells may befurther increased if additional cells, that are not used to store data,are assigned for this purpose.

One “source” of such cells is bit lines 104 in section 110, if part ofthis section is not used for ECC or for flash memory managementpurposes.

Another “source” of reference cells is portions of bit lines 104 thatare used in some word lines 106 of a block 102 and are unused in otherword lines 106, or, alternatively, are used in some blocks 102 along aword line 106 and are “free” in other blocks 102.

The situation in which some word lines 106 of a block 102 may use cellsof bit lines 104, while other word lines 106 of the block 102 do not usecells of these bit lines 102, may happen if the cells of these bit lines104 have been assigned to store block-level management data. In such acase it may not be necessary to use the cells of these bit lines 104 inall the word lines 106 of the block 102 and unused cells may be assignedto be reference cells.

Similarly, if the flash memory device includes different logical typesof blocks 102 in the same plane, some of these blocks 102 may havecertain bit lines 104 used to store data, while other blocks 102 mayhave these bit lines 104 free. One example of such a situation is aflash memory device whose blocks 102 are programmed with differentnumbers of bits-per-cell (e.g. some blocks 102 are SLC (“single levelcell”) blocks that store one bit per cell while other blocks 102 are MLC(“multi-level cell”) blocks that store two or more bits per cell, as anexample) and hence have different ECC requirements, which result indifferent numbers of bit lines 104 assigned to store ECC bits. In such acase, while MLC blocks 102 have all the bit lines 104 of section 110occupied, SLC blocks 102 have some bit lines 104 of section 110 free.

While it is conventional to use reference cells in a flash memory devicefor estimating threshold voltage drift, the cells that are used for thatpurpose are cells that are both pre-assigned as reference cells andlocated on dedicated bit lines. The technology described herein usesreference cells that are either not pre-assigned as reference cells ornot located on dedicated bit lines, specifically according to thefollowing configurations—

-   A. Within a given block 102 and on the same bit line 104, some cells    are used as management data cells and other cells are used as    reference cells. Example—having some cells in management section 110    of one word line 106 of a block 102 store control information, while    the corresponding cells in the other word lines 106 of the block 102    are used as reference cells.-   B. Within a given flash memory die and on corresponding bit lines    104 in different blocks 102 (even in the same plane), some cells are    used as management data cells and other cells used as reference    cells. Example—blocks 102 used in MLC mode store ECC parity bits in    the cells of some bit lines 104, while the cells of corresponding    bit lines 104 (or of the same bit lines 104) in blocks 102 used in    SLC mode are used as reference cells.-   C. Within a given lot of flash dies (including within the dies of    the same wafer), the cells of some bit lines 104 are used as data    cells and the cells of other bit lines 104 used as reference cells.    Example—one flash die having a large number of bad bit lines 104    causing almost all the redundant bit lines 104 of section 112 to be    used as data bit lines, while in another flash die almost all bit    lines 104 are good ones and the redundant bit lines 104 of section    112 are used as reference cells.

FIG. 3 is a high-level block diagram of a system 200 in which the ad hocdesignation of reference cells of a flash memory is effected bysoftware. System 200 includes a processor 202 and four memory devices: aRAM 204, a boot ROM 206, a mass storage device (hard disk) 208 and aflash memory device of FIG. 1 as a flash memory device 212, allcommunicating via a common bus 214. In system 200, controller 20 offlash memory device 212 functions only as an interface to bus 214; therest of the functionality of flash controller 20 of FIG. 1 as describedabove is emulated by flash memory driver code 210 that is stored in massstorage device 208 and that is executed by processor 202 to interfacebetween user applications executed by processor 202 and flash memorydevice 212, and to manage the flash memory of flash memory device 212.In addition to the conventional functionality of such flash managementdriver code, driver code 210 emulates the functionality of controller 20of FIG. 1 with respect to using, as reference cells, cells of memorycell array 1 that otherwise would not be used for any purpose, asdescribed above. Driver code 210 typically is included in operatingsystem code for system 200 but also could be freestanding code.

The components of system 200 other than flash memory device 212constitute a host 220 of flash memory device 212. Mass storage device208 is an example of a computer-readable storage medium bearingcomputer-readable driver code for using, as reference cells of a flashmemory array, cells of the flash memory array that otherwise would notbe used for any purpose. Other examples of such computer-readablestorage media include read-only memories such as CDs bearing such code.

A limited number of embodiments of methods for ad hoc designation ofreference cells of a flash memory, and of a device and system that usethe methods, have been described. It will be appreciated that manyvariations, modifications and other applications of the methods, deviceand system may be made.

1. A method of managing a nonvolatile memory that includes a pluralityof cells organized in a plurality of bit lines and a plurality of wordlines, the method comprising: (a) storing user data in respectiveportions of the cells of each of two of the word lines; and (b) in oneof the bit lines that is shared by the two word lines: (i) storingcontrol information in a cell corresponding to the one bit line and afirst of the two word lines, and (ii) using a cell corresponding to theone bit line and a second of the two word lines as a reference cell. 2.The method of claim 1, wherein the user data are stored only in cellsother than the cells of the one bit line that includes the referencecell.
 3. The method of claim 1, wherein the first and second word linesare in a common block of the nonvolatile memory.
 4. The method of claim3, wherein said control information is block-level managementinformation for managing the common block.
 5. The method of claim 1,wherein the first and second word lines are in separate respectiveblocks of the nonvolatile memory.
 6. The method of claim 5, wherein thecontrol information is error correction code information.
 7. Acontroller, for a flash memory that includes a plurality of cellsorganized in a plurality of bit lines and a plurality of word lines, thecontroller being operative: (a) to store user data in respectiveportions of the cells of each of two of the word lines; and (b) in oneof the bit lines that is shared by the two word lines: (i) to storecontrol information in a cell corresponding to the one bit line and afirst of the two word lines, and (ii) to use a cell corresponding to theone bit line and a second of two word lines as a reference cell.
 8. Aflash memory device comprising: (a) a flash memory including a pluralityof cells organized in a plurality of bit lines and a plurality of wordlines; and (b) a controller operative: (i) to store user data inrespective portions of the cells of each of two of the word lines, and(ii) in one of the bit lines that is shared by the two word lines: (A)to store control information in a cell corresponding to the one bit lineand a first of the two word lines, and (B) to use a cell correspondingto the one bit line and a second of two word lines as a reference cell.9. A system comprising: (a) a flash memory including a plurality ofcells organized in a plurality of bit lines and a plurality of wordlines; (b) a host, of the flash memory, including: (i) a memory forstoring code for managing the flash memory by steps including: (A)storing user data in respective portions of the cells of each of two ofthe word lines, and (B) in one of the bit lines that is shared by thetwo word lines: (I) storing control information in a cell correspondingto the one bit line and a first of the two word lines, and (II) using acell corresponding to the one bit line and a second of the two wordlines as a reference cell, and (ii) a processor for executing the code.10. A computer-readable storage medium having embodied thereoncomputer-readable code for managing a flash memory that includes aplurality of cells organized in a plurality of bit lines and a pluralityof word lines, the computer-readable code comprising: (a) program codefor storing user data in respective portions of the cells of each of twoof the word lines; and (b) program code for, in one of the bit linesthat is shared by the two word lines: (i) storing control information ina cell corresponding to the one bit line and a first of the two wordlines, and (ii) using a cell corresponding to the one bit line and asecond of the two word lines as a reference cell.